Fractional-N phase-locked loops (PLLs) can be used for synthesizing frequencies at a non-integer scalar frequency of an input reference signal. Phase coherent means that the phase relationship between the input reference signal and the output signal is deterministic. However, it has been found in existing fractional-N PLLs that when the PLL tunes away from one frequency to another frequency and returns to the original frequency, the relationship between the phase of the output signal and the phase of the input reference signal is not phase coherent. In other words, when changing from a frequency A to a frequency B and then back to the frequency A signal, the phase of the frequency A signal is not necessarily matched to that of the previously generated frequency A signal. Further, with existing fractional-N phase-locked loops, the phase difference between an originally-generated frequency A signal and a subsequently-generated frequency A signal may be significantly more than a rounding error of a few degrees.
In fractional-N PLL architectures, a DSM can be used to generate a sequence that enables fractional reference frequency tuning of a voltage-controlled or digitally-controlled oscillator. The DSM reduces the magnitude of fractional spurs near the PLL carrier in comparison to single accumulator fractional-N PLLs. For phase coherency, the PLL should return to the same phase relative to the PLL reference. However, DSMs may have hidden states that cause the PLL to return to a random phase relative to the reference when tuning away from a frequency and back again. This occurrence may break phase coherency. Phase coherency is important when considering multiple instances of the frequency synthesizers in a system.
U.S. Pat. No. 8,115,519, which is incorporated in this disclosure by reference in its entirety, discloses a phase accumulator that generates phase data for a direct digital synthesis (DDS) device based on a reference phase to provide analog sinusoidal outputs that are locked to the reference phase, and thus are phase coherent. The frequency of a sinusoidal DDS output may be controlled by changing a frequency control word (FCW) provided to the phase accumulator, without affecting the incrementing reference phase. The sinusoidal DDS output is based on a multiple of the FCW and the reference phase, and thus remains locked to the reference phase, providing phase coherency even when the FCW changes to change the frequency.
U.S. Pat. No. 8,664,990, which is incorporated in this disclosure by reference in its entirety, discloses a fractional-N phase-locked loop (PLL) in which the frequency control word multiplies by the output of a reference counter to provide the carry bit utilized in n/n+1 switching.